FinFET logic devices include a source region and a drain region. A gate is present over at least a portion of each of the fins. The gate regulates charge flow between the source region and the drain region through the channel regions.
FinFET density scaling is limited in the gate direction by gate pitch. Gate pitch is limited by the space required to fit the gate length, spacers, and source and drain contacts. Gate length is limited by electrostatic control of the channel.
Given these design constraints, improved techniques for finFET density scaling would be desirable.